Certain types of electronic devices have strict requirements on allowable power consumption. For example, it is desirable for implantable medical devices to have a long battery life to avoid subjecting the patient to a surgical procedure for battery replacement. Consequently, circuits used in such devices are generally developed to use as little power as possible while providing the desired functionality.
One way to reduce power consumption of a device is by lowering the operating voltage of circuits employed in the device. However, it may be impractical for all of the circuits in a given device to use a lower operating voltage. In such a case, level shifters may be used to interface between circuits operating at lower voltages and circuits operating at higher voltages.
FIG. 1 illustrates an example of a level shifter 100 that translates a digital signal from one voltage domain to another. The input IN of the level shifter 100 is in the low voltage domain and the output OUT is in the high voltage domain. Specifically, the low voltage domain lies between VSS and VDDL and the high voltage domain lies between VSS and VDDH.
The level shifter 100 consists of a latch which, through positive feedback, latches to the higher voltage domain (VDDH) to provide the output signal OUT. The lower voltage domain input signal IN drives a circuit which overcomes the current state of the latch, thereby causing the latch to switch between its bi-stable states whenever the input signal IN switches states.
The core of the level shifter 100 is comprised of transistors M1 through M4. PMOS transistors M1 and M2 comprise the latch. The transistors M1 and M2 are cross-coupled.
NMOS transistors M3 and M4 are used to initiate a switch in the state of the latch between its two bistable states. The transistors M3 and M4 are driven by the complementary input signal INp and INn. Therefore, when the transistor M3 is on (low impedance), the transistor M4 is off (high impedance) and vice versa.
The transistors are sized to enable the lower voltage transistors M3 and M4 to overpower the latch transistors M1 and M2. The transistors M1 and M2 are generally of the same size, as are the transistors M3 and M4. The ratio of the sizing of the NMOS pair (M3 and M4) to the PMOS pair (M1 and M2) controls the conditions under which the level shifter 100 shifts between different states. To start the latching action, the NMOS transistor that currently has its gate driven to VDDL must be able to overpower the PMOS transistor that currently has its gate-to-source voltage (Vgs) driven to VDDH. Thus, assuming equal transconductances of the NMOS and PMOS transistors, the aspect ratio (W/L) of the NMOS transistor must generally be larger than the aspect ratio of the PMOS transistor. Furthermore, to enable proper level shifting operation, a larger ratio between the NMOS and PMOS transistors is employed in devices that employ a larger difference between VDDH and VDDL.
There are several problems associated with conventional level shifters such as the level shifter of FIG. 1. In particular, such level shifters may not provide a desired level of performance over different input signal levels.
A level shifter designed for a specific VDDH level and a specific VDDL level (e.g., by sizing of the transistors) is not optimized for other VDDH and VDDL levels. For example, a level shifter optimized for a large VDDH to VDDL ratio, may operate too slowly for a lesser VDDH to VDDL difference. Here, since transistors have minimum allowable dimensions, either the width or the length of the transistor is usually fixed when trying to achieve large width to length ratios. Thus, if a higher ratio between the NMOS and PMOS transistors is desired to accommodate a larger VDDH to VDDL ratio, a larger NMOS transistor is called for. However, an increase in transistor size leads to more parasitic capacitances in the transistor. More parasitic capacitance, in turn, reduces the speed at which the level shifter is able to effectively operate.
Another problem with conventional level shifters occurs when the low voltage domain lies below the threshold voltage (sub-threshold) of the driving transistors. The “on” state or low impedance state of a transistor is usually associated with gate to source voltages greater than the transistor's threshold voltage, Vt. Vt may be the order of, for example, ½ volt to 1 volt for certain types of CMOS transistors. In strong inversion, to a first order, the dc output current to input gate drive (transconductance) is a linear function of Vgs when in saturation. This makes the sizing relatively simple when operating in strong inversion (i.e., non-sub-threshold).
In contrast, there is an exponential dependence upon the drive strength of a transistor operating in sub-threshold. As the voltage level of the low voltage domain is reduced below the threshold of the transistors, the size ratio between the NMOS and PMOS transistors needs to increase exponentially to ensure that the low voltage transistors (with exponentially decaying drive strength) can still overdrive the latch. Thus, if the low voltage domain is at a very low level (e.g., VDDL is <<Vt), the size ratio needed between the latch and low voltage transistors may be unfeasible. On the other hand, if the circuit is sized for a specific low and high voltage that is feasible, any change from these voltages may render the level shifter non-functional or sacrifice on speed and power.
One way of lowering the transistor size ratios in the level shifter of FIG. 1 is to employ two additional PMOS transistors above the transistors M1 and M2. One of these transistors is deployed between VDDH and the source of the transistor M1 and the other transistor is deployed between VDDH and the source of the transistor M2. These transistors are driven by the input INp and INn and thereby tend to reduce the drive strength of the latch so that lower NMOS to PMOS size ratios are needed. This has the effect of increasing the operable VDDH to VDDL range. However, even this circuit is not suitable for large VDDH to VDDL ranges since the same exponential ratios between the transistor pair M3 and M4 and the additional transistor pair are needed for sub-threshold operation.